1. Field of the Invention
The invention relates to the field of dynamic MOS RAMS and in particular to refreshing or regeneration means for such memories.
2. Prior Art
In metal-oxide-semiconductors (MOS) integrated circuit random-access memories (RAM) capacitive storage memory cells are frequently employed. In these dynamic memory cells information is stored in the form of an electrical charge on a capacitance means. These memory cells provide lower power storage and are suitable for higher density fabrication than static memory cells.
Since capacitance storage is dynamic, that is, the charge representing a binary state quickly disipates, periodic refreshing or regeneration is required. This refreshing is accomplished (in other than the planar refreshable memories) by refreshing the memory cells located along a single column line or row line in the memory. For a general discussion of this technique see U.S. Pat. No. 3,599,180. In recent years, the storage capacity and particularly the storage density of dynamic RAMS has been on a continuing increase. This increase has required longer refresh cycles.
Some dynamic RAMS known in the art are capable of "planar refreshing," that is, the entire memory array is simultaneously refreshed. However, the memory cells employed in such memories are substantially larger than the memory cells employed in other dynamic RAMS. For an example of a planar refreshable memory which does not require synchronization of the refreshing signal and memory access signal, see U.S. Pat. No. 3,858,185.
Other problems associated with the refreshing of dynamic RAMS are discussed in U.S. Pat. No. 3,806,898 and U.S. Pat. No. 3,760,379.
As will be seen the invented apparatus permits simultaneous refreshing of cells located along two lines of the memory, thereby reducing the refreshing time required by prior art dynamic MOS RAMS.